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翻訳と辞書　辞書検索 [ 開発暫定版 ] スポンサード リンク OpenRISC 1200 ： ウィキペディア英語版 OpenRISC 1200 The OpenRISC 1200 (OR1200) is an implementation of the open source OpenRISC 1000 RISC architecture (). A synthesizable CPU core, it is maintained by developers at OpenCores.org; and the Verilog RTL description is released under the GNU Lesser General Public License (LGPL). ==Architecture == The IP core of the OR1200 is implemented in the Verilog HDL. As an open source core, the design is fully public and may be downloaded and modified by any individual. The official implementation is maintained by developers at OpenCores.org. The implementation specifies a power management unit, debug unit, tick timer, programmable interrupt controller (PIC), central processing unit (CPU), and memory management hardware. Peripheral systems and a memory subsystem may be added using the processor's implementation of a standardized 32-bit Wishbone bus interface. The OR1200 is intended to have a performance comparable to an ARM10 processor architecture. 抄文引用元・出典: フリー百科事典『 ウィキペディア（Wikipedia）』 ■ウィキペディアで「OpenRISC 1200」の詳細全文を読む スポンサード リンク 翻訳と辞書 : 翻訳のためのインターネットリソース Copyright(C) kotoba.ne.jp 1997-2016. All Rights Reserved.